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Designing with Spartan-6

Are you interested in learning how to effectively utilize SpartanĀ®-6 FPGA architectural resources? This course supports both experienced and less experienced FPGA designers who have already completed the Essentials of FPGA Design course. This course focuses on understanding as well as how to properly design for the primary resources found in this popular device family.

Topics covered include device overviews, CLB construction, DCM and PLL clocking resources, global and I/O clocking techniques, memory, DSP, and source-synchronous resources. Memory controller support and the dedicated hardware resources available in each of the sub-families (PCI ExpressĀ® technology, memory controller block, and GTP transceivers) are also introduced.

This course also includes a detailed discussion about proper HDL coding techniques that enables designers to avoid common mistakes and get the most out of their FPGA. A combination of modules and labs allow for practical hands-on application of the principles taught.
After completing this comprehensive training, you will have the necessary skills to:

  • Describe all the functionality of the 6-input LUT and the CLB construction of the Spartan-6 FPGA
  • Specify the CLB resources and the available slice configurations
  • Define the block RAM and DSP resources available for the Spartan-6 FPGA
  • Properly design for the I/O block and SERDES resources
  • Identify the DCM, PLL, and clock routing resources included with this family
  • Identify the features and supported memory controllers of the hard memory controller block
  • Properly code your HDL to get the most out of the Spartan-6 FPGA
  • Describe the additional dedicated hardware for all the Spartan-6 family members