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Designing with Virtex-6

Are you interested in learning how to effectively utilize Virtex®-6 FPGA architectural resources? This course supports both experienced and less experienced FPGA designers who have already completed the Essentials of FPGA Design course. This course focuses on understanding as well as how to properly design for the primary resources found in this popular device family.

Topics covered include device overviews, CLB construction, MMCM clocking resources, global, regional and I/O clocking techniques, memory, FIFO resources, DSP, and source-synchronous resources. Soft memory controller support and the dedicated hardware resources available in each of the sub-families (EMAC, PCI Express® technology, and GTP transceivers) are also introduced

This course also includes a detailed discussion about proper HDL coding techniques that enables designers to avoid common mistakes and get the most out of their FPGA. A combination of modules and labs allow for practical hands-on application of the principles taught.
After completing this comprehensive training, you will have the necessary skills to:

  • Describe all the functionality of the 6-input LUT and the CLB construction of the Virtex-6 FPGA
  • Specify the CLB resources and the available slice configurations for the Virtex-6 FPGA
  • Define the block RAM, FIFO, and DSP resources available for the Virtex-6 FPGA
  • Properly design for the I/O block and SERDES resources
  • Identify the MMCM and clock routing resources included with this family
  • Identify the supported soft memory controllers for the Virtex-6 FPGA
  • Properly code your HDL to get the most out of the Virtex-6 FPGA
  • Describe the additional dedicated hardware for all the Virtex-6 family members