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Designing with Multi-Gigabit Serial IO

Click here to download the full Multi-Gigabit Serial IO Xilinx training course summary

Course Cost: 3 days, live with an instructor = AU$1785

Learn how to employ RocketIO™ GTP and GTX serial transceivers in your Spartan®-6 LXT or Virtex®-6 FPGA design. Understand and utilize the features of the RocketIO transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection. Additional topics include use of the Architecture Wizard, synthesis and implementation considerations, board design as it relates to the transceivers, and test and debugging. This course combines lectures with practical hands-on labs.

After completing this comprehensive training, you will have the necessary skills to:

  • Describe and utilize the ports and attributes of the RocketIO multi-gigabit transceiver in the Spartan-6 and Virtex-6 FPGA
  • Effectively utilize the following features of the GTP/GTX:
  • 8B/10B and other encoding/decoding, comma detection, clock correction, and channel bonding
  • Pre-emphasis and linear equalization
  • Use the GTP/GTX Wizard to instantiate GTP/GTX primitives
  • Access appropriate reference material for board design issues involving the power supply, reference clocking, and trace design