CPLD Essentials

This course consists of 2 packaged courses including:
• Fundamentals of CPLD Design (1 Day)
• Designing for Performance for CPLDs (1 Day)
Fundamentals of CPLD Design
This comprehensive course provides you with an introduction to designing with Xilinx CPLDs. You will learn the basics of ISE software flow and how to interpret CPLD reports for optimum performance designs.
This course covers ISE features such as the Constraints Editor and PACE. Other topics are design planning, implementation options, and global timing constraints.
Designing for Performance for CPLDs
Designing for Performance for CPLDs is an intermediate-level course that provides a comprehensive overview of the CPLD software flow. By applying the techniques presented in this course, you will be able to enhance design performance and make the best possible use of Xilinx CPLD architectures.
This course uses the ISE™ software, including the Constraints Editor & Timing Analyzer. Other topics include understanding the CPLD logic engine, estimating power, and fitting difficult designs.

