Designing for Performance

Training Course Cost: 2 days, live with an instructor = AU$990

Attending the Designing for Performance class will help you create more efficient designs. This course can help you fit your design into a smaller FPGA or a lower speed grade for reducing system costs. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your  development time, and lower development costs.

After completing this comprehensive training, you will have the necessary skills to:

  • Describe the architectural features of the Virtex-6 FPGA and Spartan-6 FPGAs
  • Create and integrate cores into your design flow by using the CORE Generatorâ„¢ software system
  • Describe the clocking features of the Virtex-6 and Spartan-6 FPGAs and how they can be used to improve performance
  • Increase performance by duplicating registers and pipelining
  • Increase system reliability by adding an appropriate synchronization circuit
  • Describe different synthesis options and how they can improve performance
  • Describe a flow for obtaining timing closure
  • Pinpoint design bottlenecks by using Timing Analyzer reports
  • Apply advanced timing constraints to meet your performance goals
  • Use advanced implementation options to increase design performance

This coure is part of the Xilinx Academy II, though can be sat individually. For course details please refer to the relevant section in the Academy II course summary:

Click here to download the full Designing for Performance Xilinx training course summary